Hangzhou-based semiconductor designer Nano-core Chip has raised over RMB 1 billion ($140 million) in a Series C2 funding round led by JianTou Investment. The new capital will fund product development and prepare the company's AI inference processors for volume production.
The announcement follows an identical RMB 1 billion Series C1 round closed just one month prior.
Why It Matters
Commercial ImplicationsAI inference demand is surging, but memory bandwidth bottlenecks limit speed and raise power consumption. By pairing RISC-V architecture with 3D near-memory and in-memory computing, Nano-core Chip aims to bypass traditional compute-memory transfer limits across edge devices and cloud servers.
The massive funding shows strong domestic support for alternative silicon architectures that reduce dependence on Western proprietary IP.
By The Numbers
Analysis & Engineering Implications for Technical Leaders
Key Developments & Takeaways
- Nano-core Chip raised more than RMB 2 billion across back-to-back C1 and C2 rounds backed by JianTou Investment, Hangzhou Capital, and Kaitai Capital.
- The startup's core silicon merges open RISC-V instruction sets with 3D near-memory and in-memory computing architectures.
- Three separate AI inference chips have completed tape-out, with customer sampling and initial volume shipments scheduled for early 2027.
What this means for enterprise teams
The facts above come from TechNode. This section is Briefzio's interpretation of their implications for architecture, cost, and vendor decisions. It is one editor's judgment, clearly separated from the reported facts.
The Big Picture
Hangzhou-based chipmaker Nano-core Chip announced it has raised over RMB 1 billion ($140 million) in Series C2 funding. The round was led by state-backed JianTou Investment, with capital coming from Hangzhou Capital, Kaitai Capital, and other regional funds.
The company will deploy the proceeds directly toward expanding product lines and preparing its manufacturing supply chains for high-volume fabrication. The fresh capital injection comes immediately after another RMB 1 billion Series C1 tranche secured in September, giving the startup a rapid cash infusion to commercialize its designs.
Hardware Architecture
Founded in 2021 out of a Peking University research institute in Zhejiang, Nano-core Chip is targeting the high-growth AI inference market rather than model training. Its engineering focus centers on breaking the memory wall that throttles large AI workloads.
- Memory Integration: The startup builds processors that combine three-dimensional near-memory computing with in-memory computing to minimize latency between storage and processing units.
- Open Standards: The architecture relies on the open RISC-V instruction set, bypassing proprietary processor architectures like ARM or x86.
- Dual Targets: The product roadmap spans both low-power edge devices and centralized hyperscale cloud facilities.
Execution Timeline
Nano-core Chip confirmed that its first three production chip designs have completed tape-out. This critical verification step proves the physical layout works before committing to expensive, full-scale wafer runs.
However, commercial deployment will require patience. The company scheduled initial customer sampling and early volume shipments for early 2027. That timeline highlights the long gestation cycle required to transition complex 3D semiconductor packages from university labs to commercial production lines.
The Road Ahead
China's venture ecosystem continues to funnel massive capital into local semiconductor startups capable of delivering hardware sovereignty. Nano-core Chip's combined RMB 2 billion haul over several weeks underscores aggressive investor appetite for domestic inference silicon.
The central hurdle moving forward is execution. Nano-core Chip must bridge the gap between working tape-outs and high-yield, cost-effective fabrication at scale before its 2027 launch window closes.
Source: TechNode
Bottom line
Analysis by Hardeep Singh
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Editor, Briefzio
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Read the analysisInitial story events referenced from TechNode. Briefzio provides independent analysis of what the reported developments mean for enterprise architecture, cost, and vendor decisions.
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Hardeep Singh is the founder and chief tech analyst at Briefzio. With a background in software engineering, distributed systems, and cloud architecture, he authors independent deep-dive technical commentary and strategic impact analyses across enterprise AI, hyperscalers, and autonomous technologies across North America.
